1. Field of the Invention
The invention relates to a stacked structure of integrated circuits, and in particular to a stacked structure of integrated circuits having reduced manufacturing cost and a miniaturized package volume.
2. Description of the Related Art
In the current technological field, every product needs to be light, thin, and small. Therefore, it is preferable that the integrated circuit has a small volume in order to meet the demands of the products. In the prior art, even if the volumes of integrated circuits are small, they only can be electrically connected to the circuit board in parallel. Because the area of the circuit board is limited, it is not possible to increase the number of the integrated circuits mounted on the circuit board. Therefore, it is difficult to make the products small, thin, and light.
To meet the demands of manufacturing small, thin, and light products, a lot of integrated circuits can be stacked. However, when a lot of integrated circuits are stacked, the upper integrated circuit will contact and press the wires of the lower integrated circuit. In this case, the signal transmission to or from the lower integrated circuit is easily influenced.
Referring to FIG. 1, a conventional stacked structure of integrated circuits includes a substrate 10, a lower integrated circuit 12, an upper integrated circuit 14, a plurality of wires 16, and a spacer layer 18. The lower integrated circuit 12 is located on the substrate 10. The spacer layer 18 is located on the lower integrated circuit 12. The upper integrated circuit 14 is stacked on the spacer layer 18. That is, the upper integrated circuit 14 is stacked above the lower integrated circuit 12 with the spacer layer 18 interposed between the integrated circuits 12 and 14. Thus, a proper gap 20 is formed between the lower integrated circuit 12 and the upper integrated circuit 14. According to this structure, the plurality of wires 16 can be electrically connected to the edge of the lower integrated circuit 12. Furthermore, the plurality of wires 16 connecting the substrate 10 to the lower integrated circuit 12 are free from being pressed when the upper integrated circuit 14 is stacked above the lower integrated circuit 12.
Please referring to FIG. 2, is a schematic illustration showing an integrated circuit formed with pads in the central region of the integrated circuit. The pads 30 are formed on the central region of the integrated circuit 32. Wires 34 are electrically connected the pads 30 to the two sides of the substrate 36, therefore, the plurality of 34 is located above the integrated circuit 32, so that such integrated circuit 32 is not stacked.